Power Saving for Merging Flip Flop Using Data Driven Clock Gating

Data-driven clock gating is reducing the total power consumption of VLSI chips. There, flip-flops are merged and share a common clock signal. Finding the optimal clusters is the key for maximizing the power savings. To reduce the hardware overhead involved, flip-flops (FFs) are merged so that they share a common clock enabling signal. Power optimization system to decrease clock power by using Multibit flips flop. Clock gating one can save power by reducing redundant clock activities confidential the clock modules. In this technique to reduce power saving by merging flip flops and integrated clock gating circuit (ICG). Our data-driven clock gating is unified into an Electronic Design Automation (EDA) profitable backend design flow, succeeding total power reduction for various types of important modern industrial and academic designs in 40 and 65 nanometer process technologies. These savings are achieved on top of the savings obtained by clock gating synthesis performed by profitable EDA tools, and gating physically inserted into the register transfer level design.